1. Field of the Invention
The present invention relates to an integrated circuit (IC) protection technique. More particularly, the present invention relates to an electrostatic discharge immunity buffer that ensures the triggering of an ESD protection circuit prior to the buffer during an ESD event.
2. Description of the Prior Art
CMOS (Complementary Metal Oxide Semiconductor) transistors are used to increase the working speed of integrated circiuts (ICs). CMOS transistors also enhance IC performance and lower the cost of each chip. In order to reduce the hot carrier effect, MOS devices have LDD structures (Lightly Doped Drain). Additionally, a "salicide" process has been developed to reduce a spreading resistance between a source or a drain and a gate. However, these processes can lead to undesired results; namely, ICs can be damaged by electrostatic discharge (ESD), making reliability a concern. ESD influences the performance of ICs in measurement, fabrication, and use. Therefore, protecting ICs from ESD damage is extremely important.
As the size of ICs decreases, the ability to protect them from ESD damage becomes more difficult. One solution is an ESD-implant process. As applied in the CMOS process, two MOS devices are formed, wherein one MOS device has LDD structures, while the other doesn't. The MOS device having LDD structures is used in an internal circuit, and the other one is used for input/output (I/O). However, the junction between a source and a drain region of the MOS device that doesn't have LDD structures and a substrate is deeper. This will cause ions in the source or the drain regions to diffuse laterally. Thus, the channel length of the MOS device must be long so as to provide adequate protection from ESD damage.
In addition, a silicided-diffusion blocking process has also been proposed to protect MOS devices from the damage caused by ESD. This process removes the silicided diffusion regions in the source and the drain regions of a MOS device so that the sheet resistance is increased. Thus, the peak current during the ESD event is limited. This results in better protection to MOS devices.
Additionally, combining the silicided-diffusion blocking process and the ESD-implant process can effectively increase the protection of CMOS ICs from damage due to ESD.
However, an additional ESD-implant mask is added in the ESD-implant process described above. The number of steps in the process and the cost are therefore increased. Further, the ESD-implant process is complex, and the salicide processing may pollute the environment. This leads to low production yield.